Adaptive power supply is an effective power-management solution for performance-power optimization in both digital and mixed-signal systems. Therefore, switched-mode regulators with fast reference tracking to provide fast change of regulated output voltages are becoming important for future IC systems. Pulse-width-modulated (PWM) switched-mode regulator is well-accepted in many mixed-signal systems, as the switching period is fixed and can be designed so that switching noise will not seriously degrade the signal-to-noise ratio of mixed-signal systems. However, PWM regulators generally have slower reference tracking due to the large and off-chip compensation capacitors for the regulator's stability. As a result, extensive parametric design on controller and compensation network is generally required to improve the tracking speed, and therefore the robustness of this approach is not high.
One type of a voltage-mode PWM buck regulator 10 to provide a regulated output voltage (VO) from an unregulated voltage (VIN) is shown in FIG. 1A, as disclosed in R. W. Erickson, Fundamentals of Power Electronics, Norwell Mass.: Kluwer Academic Publishers, 2001. The power stage 12 is formed by two power transistors (a PMOSFET: MP and a NMOSFET: MN), an inductor (LO) and a filtering capacitor (CO). The error amplifier 14 compares the reference voltage (VREF) from a voltage reference 16 with scaled VO generated by resistors 20 and 22 of respective resistances RF1 and RF2. Thus,VO=VREF·(RF1+RF2)/RF2=VREF/b                 where b=RF2/(RF1+RF2). An error voltage (Va) is then generated by error-amplifier 14 and supplied to PWM controller 24 to determine duty cycle (D) in a switching period for voltage regulation. A buck regulator operated in continuous conduction mode (CCM) has a conversion relationship given by        
            V      O              V      IN        =      D    =                            V          a                -                  V          L                                      V          H                -                  V          L                                    where VH and VL are upper and lower bounds of the ramp signal in the PWM controller 24. When VREF from reference 16 is changed, VO is changed by changing D with different Va. This change in VO is then fed through an error-amplifier 14 and a compensation network 18 that includes an off-chip compensation capacitor (CC) to the PWM controller 24. Since a large compensation capacitor (CC) is connected at the error-amplifier output for frequency compensation, the large-signal response of Va is poor and the change of VO in the prior art is therefore very slow. A dead-time control and power transistor drivers circuit 26 containing one or more power transistor driver(s) may be used to drive the power stage 12, so that there is no overlap between the times when both transistors MP and MN are on at the same time. The operation of circuits 24 and 26 is conventional and need not be described herein in detail. While the network 18 is shown to contain a single capacitor, it will be understood that it may contain more than one capacitor and one or more resistors as well to achieve one or multiple pole-zero cancellations.        
The effect of large capacitance of the compensation capacitor (CC) in compensation network 18 on tracking speed of the regulator output voltage is illustrated in FIG. 1B. As shown in FIG. 1B, the large capacitance of the compensation capacitor (CC) causes the error signal Va at the output of the error amplifier to rise slowly, so that the pulse width signal controlling the pulse width from the PWM controller 24 also causes the duty cycle (e.g. from Dn+1 to Dn+3 in FIG. 1B) and the regulator output voltage V0 to rise slowly when VREF is abruptly increased. This is undesirable.